SESC: cycle accurate architectural simulator

What is SESC?

SESC is a cycle accurate architectural simulator. It models a very wide set of architectures: single processors, CMPs, PIMs, and thread level speculation.

SESC started as the pet project of Jose Renau while doing his PhD at Urbana-Champaign in the IACOMA group. Currently, he is a new faculty at University of California, Santa Cruz.

It is used by several research groups at the University of Illinois, University of Rochester, North Carolina State University, Georgia Institute of Technology, and Cornell University.

We expect that most researchers would use SESC for their "papers". Therefore, they would be reluctant to update the cvs server with their current work. We suggest the following options:

  • Work freely with SESC as long as you want. Do not commit or report modifications while working in a paper.
  • Once you have published a paper, if and only if you want, send us the simulator extensions and we will post them in the web-site.
  • If you find a bug try to send a patch as soon as possible.
  • Add the following reference to your published papers.
    Author = {Jose Renau and Basilio Fraguela and James Tuck and Wei Liu and Milos Prvulovic and Luis Ceze and Smruti Sarangi and Paul Sack and Karin Strauss and Pablo Montesinos},
    Month = {January},
    Note = {},
    Title = {{SESC} simulator},
    Year = {2005}}
If you have any suggestion/code to improve the performance or the simulation accuracy contact us. We believe that the bigger the amount of simultaneous improvements, the better for the code quality.